| LED-TEST Project Status | |||
| Project File: | LED-Test.ise | Current State: | Programming File Generated |
| Module Name: | ledtest |
|
No Errors |
| Target Device: | xc3s500e-4fg320 |
|
55 Warnings |
| Product Version: | ISE 9.2.04i |
|
So 20. Apr 23:42:10 2008 |
| LED-TEST Partition Summary | |||
| No partition information was found. |
| Device Utilization Summary | ||||
| Logic Utilization | Used | Available | Utilization | Note(s) |
| Number of Slice Flip Flops | 52 | 9,312 | 1% | |
| Number of 4 input LUTs | 62 | 9,312 | 1% | |
| Logic Distribution | ||||
| Number of occupied Slices | 61 | 4,656 | 1% | |
| Number of Slices containing only related logic | 61 | 61 | 100% | |
| Number of Slices containing unrelated logic | 0 | 61 | 0% | |
| Total Number of 4 input LUTs | 115 | 9,312 | 1% | |
| Number used as logic | 62 | |||
| Number used as a route-thru | 53 | |||
| Number of bonded IOBs | 21 | 232 | 9% | |
| IOB Flip Flops | 12 | |||
| Number of GCLKs | 1 | 24 | 4% | |
| Number of DCMs | 1 | 4 | 25% | |
| Total equivalent gate count for design | 8,244 | |||
| Additional JTAG gate count for IOBs | 1,008 | |||
| Performance Summary | |||
| Final Timing Score: | 0 | Pinout Data: | Pinout Report |
| Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report |
| Timing Constraints: | All Constraints Met | ||
| Detailed Reports | |||||
| Report Name | Status | Generated | Errors | Warnings | Infos |
| Synthesis Report | Current | So 20. Apr 23:41:40 2008 | 0 | 39 Warnings | 0 |
| Translation Report | Current | So 20. Apr 23:41:46 2008 | 0 | 0 | 0 |
| Map Report | Current | So 20. Apr 23:41:50 2008 | 0 | 6 Warnings | 5 Infos |
| Place and Route Report | Current | So 20. Apr 23:42:01 2008 | 0 | 5 Warnings | 1 Info |
| Static Timing Report | Current | So 20. Apr 23:42:03 2008 | 0 | 0 | 2 Infos |
| Bitgen Report | Current | So 20. Apr 23:42:09 2008 | 0 | 5 Warnings | 1 Info |