Release 9.2.04i Map J.40 Xilinx Mapping Report File for Design 'ledtest' Design Information ------------------ Command Line : E:\Programme\Xilinx92i\bin\nt\map.exe -ise E:/Dokumente und Einstellungen/Johannes/Eigene Dateien/ISE Projects/LED-Test/LED-Test.ise -intstyle ise -p xc3s500e-fg320-4 -cm area -pr b -k 4 -c 100 -o ledtest_map.ncd ledtest.ngd ledtest.pcf Target Device : xc3s500e Target Package : fg320 Target Speed : -4 Mapper Version : spartan3e -- $Revision: 1.36 $ Mapped Date : Sun Apr 20 23:41:47 2008 Design Summary -------------- Number of errors: 0 Number of warnings: 6 Logic Utilization: Number of Slice Flip Flops: 52 out of 9,312 1% Number of 4 input LUTs: 62 out of 9,312 1% Logic Distribution: Number of occupied Slices: 61 out of 4,656 1% Number of Slices containing only related logic: 61 out of 61 100% Number of Slices containing unrelated logic: 0 out of 61 0% *See NOTES below for an explanation of the effects of unrelated logic Total Number of 4 input LUTs: 115 out of 9,312 1% Number used as logic: 62 Number used as a route-thru: 53 Number of bonded IOBs: 21 out of 232 9% IOB Flip Flops: 12 Number of GCLKs: 1 out of 24 4% Number of DCMs: 1 out of 4 25% Total equivalent gate count for design: 8,244 Additional JTAG gate count for IOBs: 1,008 Peak Memory Usage: 151 MB Total REAL time to MAP completion: 2 secs Total CPU time to MAP completion: 2 secs NOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design. Table of Contents ----------------- Section 1 - Errors Section 2 - Warnings Section 3 - Informational Section 4 - Removed Logic Summary Section 5 - Removed Logic Section 6 - IOB Properties Section 7 - RPMs Section 8 - Guide Report Section 9 - Area Group and Partition Summary Section 10 - Modular Design Summary Section 11 - Timing Report Section 12 - Configuration String Information Section 13 - Control Set Information Section 1 - Errors ------------------ Section 2 - Warnings -------------------- WARNING:LIT:243 - Logical network BTN0_IBUF has no load. WARNING:LIT:395 - The above warning message base_net_load_rule is repeated 2 more times for the following (max. 5 shown): BTN1_IBUF, BTN3_IBUF To see the details of these warning messages, please use the -detail switch. WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive any load pins in the design. WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive any load pins in the design. WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive any load pins in the design. WARNING:PhysDesignRules:549 - Unexpected DCM programming. For DCM comp DCM_SP_inst/DCM_SP_inst, when the CLKFX or CLKFX180 pins are used the CLKIN_PERIOD attribute must be specified in order to achieve optimal performance. Section 3 - Informational ------------------------- INFO:MapLib:562 - No environment variables are currently set. INFO:MapLib:863 - The following Virtex BUFG(s) is/are being retargeted to Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0: BUFG symbol "CLOCK_IBUFG_BUFG" (output signal=CLOCK_IBUFG) INFO:MapLib:159 - Net Timing constraints on signal CLOCK are pushed forward through input buffer. INFO:LIT:244 - All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs in the schematic. INFO:PhysDesignRules:772 - To achieve optimal frequency synthesis performance with the CLKFX and CLKFX180 outputs of the DCM comp DCM_SP_inst/DCM_SP_inst, consult the device Interactive Data Sheet. Section 4 - Removed Logic Summary --------------------------------- 2 block(s) optimized away Section 5 - Removed Logic ------------------------- Optimized Block(s): TYPE BLOCK GND XST_GND VCC XST_VCC To enable printing of redundant blocks removed and signals merged, set the detailed map report option and rerun map. Section 6 - IOB Properties -------------------------- +-----------------------------------------------------------------------------------------------------------------------------------------+ | IOB Name | IOB Type | Direction | IO Standard | Drive | Slew | Reg (s) | Resistor | IBUF/IFD | | | | | | Strength | Rate | | | Delay | +-----------------------------------------------------------------------------------------------------------------------------------------+ | BTN0 | IBUF | INPUT | LVCMOS25 | | | | PULLDOWN | 0 / 0 | | BTN1 | IBUF | INPUT | LVCMOS25 | | | | PULLDOWN | 0 / 0 | | BTN2 | IBUF | INPUT | LVCMOS25 | | | | PULLDOWN | 0 / 0 | | BTN3 | IBUF | INPUT | LVCMOS25 | | | | PULLDOWN | 0 / 0 | | CLOCK | IBUF | INPUT | LVTTL | | | | | 0 / 0 | | CLOCK_SYNTH | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | | LED0 | IOB | OUTPUT | LVTTL | 12 | SLOW | | | 0 / 0 | | LED1 | IOB | OUTPUT | LVTTL | 12 | SLOW | OFF1 | | 0 / 0 | | LED2 | IOB | OUTPUT | LVTTL | 12 | SLOW | OFF1 | | 0 / 0 | | LED3 | IOB | OUTPUT | LVTTL | 12 | SLOW | OFF1 | | 0 / 0 | | LED4 | IOB | OUTPUT | LVTTL | 12 | SLOW | OFF1 | | 0 / 0 | | LED5 | IOB | OUTPUT | LVTTL | 12 | SLOW | OFF1 | | 0 / 0 | | LED6 | IOB | OUTPUT | LVTTL | 12 | SLOW | OFF1 | | 0 / 0 | | LED7 | IOB | OUTPUT | LVTTL | 12 | SLOW | OFF1 | | 0 / 0 | | SW0 | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | SW1 | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | VGA_BLUE | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | 0 / 0 | | VGA_GREEN | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | 0 / 0 | | VGA_HS | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | 0 / 0 | | VGA_RED | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | 0 / 0 | | VGA_VS | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | 0 / 0 | +-----------------------------------------------------------------------------------------------------------------------------------------+ Section 7 - RPMs ---------------- Section 8 - Guide Report ------------------------ Guide not run on this design. Section 9 - Area Group and Partition Summary -------------------------------------------- Partition Implementation Status ------------------------------- No Partitions were found in this design. ------------------------------- Area Group Information ---------------------- No area groups were found in this design. ---------------------- Section 10 - Modular Design Summary ----------------------------------- Modular Design not used for this design. Section 11 - Timing Report -------------------------- This design was not run using timing mode. Section 12 - Configuration String Details ----------------------------------------- Use the "-detail" map option to print out Configuration Strings Section 13 - Control Set Information ------------------------------------ No control set information for this architecture.