---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 13:48:40 04/20/2008 -- Design Name: -- Module Name: ledtest - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- DCM Library UNISIM; use UNISIM.vcomponents.all; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity ledtest is Port ( CLOCK : in STD_LOGIC; SW0 : in STD_LOGIC; SW1 : in STD_LOGIC; LED0 : out STD_LOGIC; LED1 : out STD_LOGIC; LED2 : out STD_LOGIC; LED3 : out STD_LOGIC; LED4 : out STD_LOGIC; LED5 : out STD_LOGIC; LED6 : out STD_LOGIC; LED7 : out STD_LOGIC; BTN0 : in STD_LOGIC; BTN1 : in STD_LOGIC; BTN2 : in STD_LOGIC; BTN3 : in STD_LOGIC; CLOCK_SYNTH : inout STD_LOGIC; VGA_RED : out STD_LOGIC; VGA_GREEN : out STD_LOGIC; VGA_BLUE : out STD_LOGIC; VGA_HS : out STD_LOGIC; VGA_VS : out STD_LOGIC ); end ledtest; architecture Behavioral of ledtest is signal horizontal_counter : std_logic_vector (10 downto 0); signal vertical_counter : std_logic_vector (10 downto 0); signal CLK_COUNTER : std_logic_vector (63 downto 0); begin DCM_SP_inst : DCM_SP generic map ( CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 CLKFX_DIVIDE => 5, -- Can be any interger from 1 to 32 CLKFX_MULTIPLY => 4, -- Can be any integer from 1 to 32 CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature CLKIN_PERIOD => 0.0, -- Specify period of input clock CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of "NONE", "FIXED" or "VARIABLE" CLK_FEEDBACK => "1X", -- Specify clock feedback of "NONE", "1X" or "2X" DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- "SOURCE_SYNCHRONOUS", "SYSTEM_SYNCHRONOUS" or -- an integer from 0 to 15 DFS_FREQUENCY_MODE => "LOW", -- "HIGH" or "LOW" frequency mode for -- frequency synthesis DLL_FREQUENCY_MODE => "LOW", -- "HIGH" or "LOW" frequency mode for DLL DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE FACTORY_JF => X"C080", -- FACTORY JF Values PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255 STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM_SP LOCK, TRUE/FALSE port map ( -- CLK0 => CLK0, -- 0 degree DCM CLK ouptput -- CLK180 => CLK180, -- 180 degree DCM CLK output -- CLK270 => CLK270, -- 270 degree DCM CLK output -- CLK2X => CLK2X, -- 2X DCM CLK output -- CLK2X180 => CLK2X180, -- 2X, 180 degree DCM CLK out -- CLK90 => CLK90, -- 90 degree DCM CLK output -- CLKDV => CLKDV, -- Divided DCM CLK out (CLKDV_DIVIDE) CLKFX => CLOCK_SYNTH, -- DCM CLK synthesis out (M/D) -- CLKFX180 => CLKFX180, -- 180 degree CLK synthesis out -- LOCKED => LOCKED, -- DCM LOCK status output -- PSDONE => PSDONE, -- Dynamic phase adjust done output -- STATUS => STATUS, -- 8-bit DCM status bits output -- CLKFB => CLKFB, -- DCM clock feedback CLKIN => CLOCK -- Clock input (from IBUFG, BUFG or DCM) -- PSCLK => PSCLK, -- Dynamic phase adjust clock input -- PSEN => PSEN, -- Dynamic phase adjust enable input -- PSINCDEC => PSINCDEC, -- Dynamic phase adjust increment/decrement -- RST => RST -- DCM asynchronous reset input ); process(SW0, SW1) begin if ((SW0 = '1') and (SW1 = '1')) then LED0 <= '1'; else LED0 <= '0'; end if; end process; process (CLOCK, BTN2) begin if CLOCK = '1' and CLOCK'event then CLK_COUNTER <= CLK_COUNTER + 1; LED1 <= CLK_COUNTER(23); LED2 <= CLK_COUNTER(24); LED3 <= CLK_COUNTER(25); LED4 <= CLK_COUNTER(26); LED5 <= CLK_COUNTER(27); LED6 <= CLK_COUNTER(28); LED7 <= CLK_COUNTER(29); if BTN2 = '1' then CLK_COUNTER <= "0000000000000000000000000000000000000000000000000000000000000000"; end if; end if; end process; process (BTN0, BTN1, BTN2, BTN3) begin -- nix end process; process (CLOCK) variable tmp1 : std_logic_vector (10 downto 0); variable tmp2 : std_logic_vector (10 downto 0); begin -- 880x600x72 -- 50 Mhz 800hpx 56hfp 120hsp 64hbp 600vpx 37vfp 6vsp 23vbp if CLOCK'event and CLOCK = '1' then if horizontal_counter = "00010111001" -- hsp + hbp + 1 = 185 then VGA_RED <= '0'; VGA_GREEN <= '1'; VGA_BLUE <= '0'; elsif horizontal_counter = "01111011000" -- hsp + hbp + hpx = 984 then VGA_RED <= '0'; VGA_GREEN <= '1'; VGA_BLUE <= '0'; elsif vertical_counter = "00000011110" -- vsp + vbp + 1 = 30 then VGA_RED <= '0'; VGA_GREEN <= '0'; VGA_BLUE <= '1'; elsif vertical_counter = "01001110101" -- vsp + vbp + vpx = 629 then VGA_RED <= '0'; VGA_GREEN <= '0'; VGA_BLUE <= '1'; elsif (horizontal_counter > "00010111001" ) and (horizontal_counter < "01111011000" ) and (vertical_counter > "00000011110" ) and (vertical_counter < "01001110101" ) then --VGA_RED <= horizontal_counter(3) and vertical_counter(3); --VGA_GREEN <= horizontal_counter(4) and vertical_counter(4); --VGA_BLUE <= horizontal_counter(5) and vertical_counter(5); tmp1 := horizontal_counter - "00010111001"; tmp2 := vertical_counter - "00000011110"; VGA_RED <= not (tmp1(3) and tmp2(3)); VGA_GREEN <= not (tmp1(4) and tmp2(4)); VGA_BLUE <= not (tmp1(5) and tmp2(5)); else VGA_RED <= '0'; VGA_GREEN <= '0'; VGA_BLUE <= '0'; end if; if (horizontal_counter < "00001111001" ) -- hsp + 1 = 121 then VGA_HS <= '0'; VGA_RED <= '0'; VGA_GREEN <= '0'; VGA_BLUE <= '0'; else VGA_HS <= '1'; end if; if (vertical_counter < "00000000111" ) -- vsp + 1 = 7 then VGA_VS <= '0'; VGA_RED <= '0'; VGA_GREEN <= '0'; VGA_BLUE <= '0'; else VGA_VS <= '1'; end if; horizontal_counter <= horizontal_counter + "00000000001"; if (horizontal_counter = "10000010000") then -- hpx hfp hsp hbp = 1040 vertical_counter <= vertical_counter + "00000000001"; horizontal_counter <= "00000000000"; end if; if (vertical_counter = "01010011010") then -- vpx vfp vsp vbp = 666 vertical_counter <= "00000000000"; end if; end if; end process; end Behavioral;