Release 9.2.04i - par J.40
Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.

Sun Apr 20 23:42:01 2008

All signals are completely routed.

WARNING:ParHelpers:361 - There are 3 loadless signals in this design. This design will cause Bitgen to issue DRC
   warnings.

   BTN0_IBUF
   BTN1_IBUF
   BTN3_IBUF