Release 9.2.04i - xst J.40 Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to ./xst/projnav.tmp CPU : 0.00 / 0.17 s | Elapsed : 0.00 / 1.00 s --> Parameter xsthdpdir set to ./xst CPU : 0.00 / 0.17 s | Elapsed : 0.00 / 1.00 s --> Reading design: ledtest.prj TABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Compilation 3) Design Hierarchy Analysis 4) HDL Analysis 5) HDL Synthesis 5.1) HDL Synthesis Report 6) Advanced HDL Synthesis 6.1) Advanced HDL Synthesis Report 7) Low Level Synthesis 8) Partition Report 9) Final Report 9.1) Device utilization summary 9.2) Partition Resource Summary 9.3) TIMING REPORT ========================================================================= * Synthesis Options Summary * ========================================================================= ---- Source Parameters Input File Name : "ledtest.prj" Input Format : mixed Ignore Synthesis Constraint File : NO ---- Target Parameters Output File Name : "ledtest" Output Format : NGC Target Device : xc3s500e-4-fg320 ---- Source Options Top Module Name : ledtest Automatic FSM Extraction : YES FSM Encoding Algorithm : Auto Safe Implementation : No FSM Style : lut RAM Extraction : Yes RAM Style : Auto ROM Extraction : Yes Mux Style : Auto Decoder Extraction : YES Priority Encoder Extraction : YES Shift Register Extraction : YES Logical Shifter Extraction : YES XOR Collapsing : YES ROM Style : Auto Mux Extraction : YES Resource Sharing : YES Asynchronous To Synchronous : NO Multiplier Style : auto Automatic Register Balancing : No ---- Target Options Add IO Buffers : YES Global Maximum Fanout : 500 Add Generic Clock Buffer(BUFG) : 24 Register Duplication : YES Slice Packing : YES Optimize Instantiated Primitives : NO Use Clock Enable : Yes Use Synchronous Set : Yes Use Synchronous Reset : Yes Pack IO Registers into IOBs : auto Equivalent register Removal : YES ---- General Options Optimization Goal : Speed Optimization Effort : 1 Library Search Order : ledtest.lso Keep Hierarchy : NO RTL Output : Yes Global Optimization : AllClockNets Read Cores : YES Write Timing Constraints : NO Cross Clock Analysis : NO Hierarchy Separator : / Bus Delimiter : <> Case Specifier : maintain Slice Utilization Ratio : 100 BRAM Utilization Ratio : 100 Verilog 2001 : YES Auto BRAM Packing : NO Slice Utilization Ratio Delta : 5 ========================================================================= ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file "E:/Dokumente und Einstellungen/Johannes/Eigene Dateien/ISE Projects/LED-Test/ledtest.vhd" in Library work. Entity compiled. Entity (Architecture ) compiled. ========================================================================= * Design Hierarchy Analysis * ========================================================================= Analyzing hierarchy for entity in library (architecture ). ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity in library (Architecture ). Set user-defined property "CLK_FEEDBACK = 1X" for instance in unit . Set user-defined property "CLKDV_DIVIDE = 2.0000000000000000" for instance in unit . Set user-defined property "CLKFX_DIVIDE = 5" for instance in unit . Set user-defined property "CLKFX_MULTIPLY = 4" for instance in unit . Set user-defined property "CLKIN_DIVIDE_BY_2 = FALSE" for instance in unit . Set user-defined property "CLKIN_PERIOD = 0.0000000000000000" for instance in unit . Set user-defined property "CLKOUT_PHASE_SHIFT = NONE" for instance in unit . Set user-defined property "DESKEW_ADJUST = SYSTEM_SYNCHRONOUS" for instance in unit . Set user-defined property "DFS_FREQUENCY_MODE = LOW" for instance in unit . Set user-defined property "DLL_FREQUENCY_MODE = LOW" for instance in unit . Set user-defined property "DSS_MODE = NONE" for instance in unit . Set user-defined property "DUTY_CYCLE_CORRECTION = TRUE" for instance in unit . Set user-defined property "FACTORY_JF = C080" for instance in unit . Set user-defined property "PHASE_SHIFT = 0" for instance in unit . Set user-defined property "STARTUP_WAIT = FALSE" for instance in unit . Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Performing bidirectional port resolution... Synthesizing Unit . Related source file is "E:/Dokumente und Einstellungen/Johannes/Eigene Dateien/ISE Projects/LED-Test/ledtest.vhd". WARNING:Xst:647 - Input is never used. WARNING:Xst:647 - Input is never used. WARNING:Xst:647 - Input is never used. WARNING:Xst:2734 - Property "use_dsp48" is not applicable for this technology. WARNING:Xst:2734 - Property "use_dsp48" is not applicable for this technology. Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 64-bit up counter for signal . Found 11-bit up counter for signal . Found 11-bit subtractor for signal created at line 174. Found 11-bit subtractor for signal created at line 175. Found 11-bit up counter for signal . Found 11-bit comparator greater for signal created at line 165. Found 11-bit comparator greater for signal created at line 165. Found 11-bit comparator less for signal created at line 165. Found 11-bit comparator less for signal created at line 165. Found 11-bit comparator less for signal created at line 184. Found 11-bit comparator less for signal created at line 193. Summary: inferred 3 Counter(s). inferred 12 D-type flip-flop(s). inferred 2 Adder/Subtractor(s). inferred 6 Comparator(s). Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # Adders/Subtractors : 2 11-bit subtractor : 2 # Counters : 3 11-bit up counter : 2 64-bit up counter : 1 # Registers : 12 1-bit register : 12 # Comparators : 6 11-bit comparator greater : 2 11-bit comparator less : 4 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Loading device for application Rf_Device from file '3s500e.nph' in environment E:\Programme\Xilinx92i. ========================================================================= Advanced HDL Synthesis Report Macro Statistics # Adders/Subtractors : 2 6-bit subtractor : 2 # Counters : 3 11-bit up counter : 2 64-bit up counter : 1 # Registers : 12 Flip-Flops : 12 # Comparators : 6 11-bit comparator greater : 2 11-bit comparator less : 4 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . Optimizing unit ... Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block ledtest, actual ratio is 1. Final Macro Processing ... ========================================================================= Final Register Report Macro Statistics # Registers : 64 Flip-Flops : 64 ========================================================================= ========================================================================= * Partition Report * ========================================================================= Partition Implementation Status ------------------------------- No Partitions were found in this design. ------------------------------- ========================================================================= * Final Report * ========================================================================= Final Results RTL Top Level Output File Name : ledtest.ngr Top Level Output File Name : ledtest Output Format : NGC Optimization Goal : Speed Keep Hierarchy : NO Design Statistics # IOs : 21 Cell Usage : # BELS : 238 # GND : 1 # INV : 9 # LUT1 : 53 # LUT2 : 9 # LUT2_L : 3 # LUT3 : 7 # LUT3_D : 2 # LUT3_L : 2 # LUT4 : 26 # LUT4_D : 3 # LUT4_L : 3 # MUXCY : 68 # MUXF5 : 2 # VCC : 1 # XORCY : 49 # FlipFlops/Latches : 64 # FD : 7 # FDR : 45 # FDRE : 11 # FDRS : 1 # Clock Buffers : 1 # BUFG : 1 # IO Buffers : 18 # IBUF : 3 # IBUFG : 1 # OBUF : 14 # DCMs : 1 # DCM_SP : 1 ========================================================================= Device utilization summary: --------------------------- Selected Device : 3s500efg320-4 Number of Slices: 62 out of 4656 1% Number of Slice Flip Flops: 64 out of 9312 0% Number of 4 input LUTs: 117 out of 9312 1% Number of IOs: 21 Number of bonded IOBs: 18 out of 232 7% Number of GCLKs: 1 out of 24 4% Number of DCMs: 1 out of 4 25% --------------------------- Partition Resource Summary: --------------------------- No Partitions were found in this design. --------------------------- ========================================================================= TIMING REPORT NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE. Clock Information: ------------------ -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ CLOCK | IBUFG+BUFG | 64 | -----------------------------------+------------------------+-------+ Asynchronous Control Signals Information: ---------------------------------------- No asynchronous control signals found in this design Timing Summary: --------------- Speed Grade: -4 Minimum period: 6.312ns (Maximum Frequency: 158.428MHz) Minimum input arrival time before clock: 3.391ns Maximum output required time after clock: 4.283ns Maximum combinational path delay: 6.209ns Timing Detail: -------------- All values displayed in nanoseconds (ns) ========================================================================= Timing constraint: Default period analysis for Clock 'CLOCK' Clock period: 6.312ns (frequency: 158.428MHz) Total number of paths / destination ports: 1316 / 101 ------------------------------------------------------------------------- Delay: 6.312ns (Levels of Logic = 5) Source: horizontal_counter_10 (FF) Destination: VGA_BLUE (FF) Source Clock: CLOCK rising Destination Clock: CLOCK rising Data Path: horizontal_counter_10 to VGA_BLUE Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FDR:C->Q 6 0.591 0.844 horizontal_counter_10 (horizontal_counter_10) LUT3:I0->O 2 0.704 0.526 VGA_BLUE_and00012 (VGA_BLUE_and0001_map1) LUT3:I1->O 1 0.704 0.000 VGA_BLUE_and0001101_SW0_F (N239) MUXF5:I0->O 2 0.321 0.451 VGA_BLUE_and0001101_SW0 (N226) LUT4_D:I3->O 1 0.704 0.455 VGA_BLUE_and0001101 (VGA_BLUE_and0001) LUT4:I2->O 1 0.704 0.000 VGA_BLUE_mux000992 (VGA_BLUE_mux0009) FDR:D 0.308 VGA_BLUE ---------------------------------------- Total 6.312ns (4.036ns logic, 2.276ns route) (63.9% logic, 36.1% route) ========================================================================= Timing constraint: Default OFFSET IN BEFORE for Clock 'CLOCK' Total number of paths / destination ports: 30 / 30 ------------------------------------------------------------------------- Offset: 3.391ns (Levels of Logic = 1) Source: BTN2 (PAD) Destination: CLK_COUNTER_0 (FF) Destination Clock: CLOCK rising Data Path: BTN2 to CLK_COUNTER_0 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ IBUF:I->O 30 1.218 1.262 BTN2_IBUF (BTN2_IBUF) FDR:R 0.911 CLK_COUNTER_0 ---------------------------------------- Total 3.391ns (2.129ns logic, 1.262ns route) (62.8% logic, 37.2% route) ========================================================================= Timing constraint: Default OFFSET OUT AFTER for Clock 'CLOCK' Total number of paths / destination ports: 12 / 12 ------------------------------------------------------------------------- Offset: 4.283ns (Levels of Logic = 1) Source: VGA_HS (FF) Destination: VGA_HS (PAD) Source Clock: CLOCK rising Data Path: VGA_HS to VGA_HS Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FDR:C->Q 1 0.591 0.420 VGA_HS (VGA_HS_OBUF) OBUF:I->O 3.272 VGA_HS_OBUF (VGA_HS) ---------------------------------------- Total 4.283ns (3.863ns logic, 0.420ns route) (90.2% logic, 9.8% route) ========================================================================= Timing constraint: Default path analysis Total number of paths / destination ports: 4 / 3 ------------------------------------------------------------------------- Delay: 6.209ns (Levels of Logic = 3) Source: SW0 (PAD) Destination: LED0 (PAD) Data Path: SW0 to LED0 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ IBUF:I->O 1 1.218 0.595 SW0_IBUF (SW0_IBUF) LUT2:I0->O 1 0.704 0.420 LED0_and00001 (LED0_OBUF) OBUF:I->O 3.272 LED0_OBUF (LED0) ---------------------------------------- Total 6.209ns (5.194ns logic, 1.015ns route) (83.7% logic, 16.3% route) ========================================================================= CPU : 6.59 / 6.78 s | Elapsed : 6.00 / 7.00 s --> Total memory usage is 155324 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 39 ( 0 filtered) Number of infos : 0 ( 0 filtered)