Release 9.2.04i par J.40 Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved. IMPIC:: Sun Apr 20 23:41:51 2008 par -w -intstyle ise -ol std -t 1 ledtest_map.ncd ledtest.ncd ledtest.pcf Constraints file: ledtest.pcf. Loading device for application Rf_Device from file '3s500e.nph' in environment E:\Programme\Xilinx92i. "ledtest" is an NCD, version 3.1, device xc3s500e, package fg320, speed -4 Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 100.000 Celsius) Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.320 Volts) Device speed data version: "PRODUCTION 1.27 2007-10-19". Design Summary Report: Number of External IOBs 21 out of 232 9% Number of External Input IOBs 7 Number of External Input IBUFs 7 Number of LOCed External Input IBUFs 7 out of 7 100% Number of External Output IOBs 14 Number of External Output IOBs 14 Number of LOCed External Output IOBs 13 out of 14 92% Number of External Bidir IOBs 0 Number of BUFGMUXs 1 out of 24 4% Number of DCMs 1 out of 4 25% Number of Slices 61 out of 4656 1% Number of SLICEMs 0 out of 2328 0% Overall effort level (-ol): Standard Placer effort level (-pl): High Placer cost table entry (-t): 1 Router effort level (-rl): Standard Starting initial Timing Analysis. REAL time: 1 secs Finished initial Timing Analysis. REAL time: 1 secs WARNING:Par:288 - The signal BTN0_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal BTN1_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal BTN3_IBUF has no load. PAR will not attempt to route this signal. Starting Placer Phase 1.1 Phase 1.1 (Checksum:989865) REAL time: 1 secs Phase 2.7 INFO:Place:834 - Only a subset of IOs are locked. Out of 14 IOs, 13 are locked and 1 are not locked. If you would like to print the names of these IOs, please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1. Phase 2.7 (Checksum:1312cfe) REAL time: 1 secs Phase 3.31 Phase 3.31 (Checksum:1c9c37d) REAL time: 1 secs Phase 4.2 ...... Phase 4.2 (Checksum:98a2ff) REAL time: 2 secs Phase 5.30 Phase 5.30 (Checksum:2faf07b) REAL time: 2 secs Phase 6.3 Phase 6.3 (Checksum:39386fa) REAL time: 2 secs Phase 7.5 Phase 7.5 (Checksum:42c1d79) REAL time: 2 secs Phase 8.8 .. . .. . . . Phase 8.8 (Checksum:9a0947) REAL time: 5 secs Phase 9.5 Phase 9.5 (Checksum:55d4a77) REAL time: 5 secs Phase 10.18 Phase 10.18 (Checksum:5f5e0f6) REAL time: 5 secs Phase 11.5 Phase 11.5 (Checksum:68e7775) REAL time: 5 secs REAL time consumed by placer: 5 secs CPU time consumed by placer: 5 secs Writing design to file ledtest.ncd Total REAL time to Placer completion: 5 secs Total CPU time to Placer completion: 5 secs Starting Router Phase 1: 383 unrouted; REAL time: 8 secs Phase 2: 332 unrouted; REAL time: 8 secs Phase 3: 56 unrouted; REAL time: 8 secs Phase 4: 56 unrouted; (0) REAL time: 8 secs Phase 5: 56 unrouted; (0) REAL time: 8 secs Phase 6: 56 unrouted; (0) REAL time: 8 secs Phase 7: 0 unrouted; (0) REAL time: 8 secs Phase 8: 0 unrouted; (0) REAL time: 8 secs Total REAL time to Router completion: 8 secs Total CPU time to Router completion: 8 secs Partition Implementation Status ------------------------------- No Partitions were found in this design. ------------------------------- Generating "PAR" statistics. ************************** Generating Clock Report ************************** +---------------------+--------------+------+------+------------+-------------+ | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| +---------------------+--------------+------+------+------------+-------------+ | CLOCK_IBUFG | BUFGMUX_X1Y11| No | 39 | 0.055 | 0.190 | +---------------------+--------------+------+------+------------+-------------+ * Net Skew is the difference between the minimum and maximum routing only delays for the net. Note this is different from Clock Skew which is reported in TRCE timing report. Clock Skew is the difference between the minimum and maximum path delays which includes logic delays. The Delay Summary Report The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0 The AVERAGE CONNECTION DELAY for this design is: 0.786 The MAXIMUM PIN DELAY IS: 3.541 The AVERAGE CONNECTION DELAY on the 10 WORST NETS is: 2.059 Listing Pin Delays by value: (nsec) d < 1.00 < d < 2.00 < d < 3.00 < d < 4.00 < d < 5.00 d >= 5.00 --------- --------- --------- --------- --------- --------- 243 109 14 3 0 0 Timing Score: 0 Asterisk (*) preceding a constraint indicates it was not met. This may be due to a setup or hold violation. ------------------------------------------------------------------------------------------------------ Constraint | Check | Worst Case | Best Case | Timing | Timing | | Slack | Achievable | Errors | Score ------------------------------------------------------------------------------------------------------ NET "CLOCK_IBUFG1" PERIOD = 20 ns HIGH 50 | SETUP | 12.061ns| 7.939ns| 0| 0 % | HOLD | 1.043ns| | 0| 0 ------------------------------------------------------------------------------------------------------ All constraints were met. Generating Pad Report. All signals are completely routed. WARNING:Par:283 - There are 3 loadless signals in this design. This design will cause Bitgen to issue DRC warnings. Total REAL time to PAR completion: 9 secs Total CPU time to PAR completion: 9 secs Peak Memory Usage: 136 MB Placement: Completed - No errors found. Routing: Completed - No errors found. Timing: Completed - No errors found. Number of error messages: 0 Number of warning messages: 5 Number of info messages: 1 Writing design to file ledtest.ncd PAR done!