Logical network BTN0_IBUF has no load. The above warning message base_net_load_rule is repeated 2 more times for the following (max. 5 shown): BTN1_IBUF, BTN3_IBUF To see the details of these warning messages, please use the -detail switch. No environment variables are currently set. The following Virtex BUFG(s) is/are being retargeted to Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0: BUFG symbol "CLOCK_IBUFG_BUFG" (output signal=CLOCK_IBUFG) Net Timing constraints on signal CLOCK are pushed forward through input buffer. All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs in the schematic. The signal <BTN0_IBUF> is incomplete. The signal does not drive any load pins in the design. The signal <BTN1_IBUF> is incomplete. The signal does not drive any load pins in the design. The signal <BTN3_IBUF> is incomplete. The signal does not drive any load pins in the design. To achieve optimal frequency synthesis performance with the CLKFX and CLKFX180 outputs of the DCM comp DCM_SP_inst/DCM_SP_inst, consult the device Interactive Data Sheet. Unexpected DCM programming. For DCM comp DCM_SP_inst/DCM_SP_inst, when the CLKFX or CLKFX180 pins are used the CLKIN_PERIOD attribute must be specified in order to achieve optimal performance.