The signal <BTN0_IBUF> is incomplete. The signal does not drive any load pins in the design. The signal <BTN1_IBUF> is incomplete. The signal does not drive any load pins in the design. The signal <BTN3_IBUF> is incomplete. The signal does not drive any load pins in the design. To achieve optimal frequency synthesis performance with the CLKFX and CLKFX180 outputs of the DCM comp DCM_SP_inst/DCM_SP_inst, consult the device Interactive Data Sheet. Unexpected DCM programming. For DCM comp DCM_SP_inst/DCM_SP_inst, when the CLKFX or CLKFX180 pins are used the CLKIN_PERIOD attribute must be specified in order to achieve optimal performance. CLKIN_PERIOD is set to 0 ps which is less than the minimum of 3067 ps. The CLKIN_PERIOD is the period of the input clock to the DCM. The CLKIN_PERIOD is used by the DCM for frequency synthesis. To set the CLKIN_PERIOD in the UCF use the syntax: INST "DCM instance name" CLKIN_PERIOD=X ns;